Appendix: YM7128 Surround Processor (SP2)

Yamaha YM7128 (SP2) surround-processor datasheet and the bit-serial protocol used to program it.

Introduction

This section briefly describes how to program the Yamaha YM7128 Surround Processor (SP2) on the Gold Card.

A first section describes the method used to access the SP2 chip through the Control Chip on the Ad Lib Gold card.

The second part is a hardware description of the SP2 chip.

Sample source code is also available in the Developer Toolkit disk, in the <SURROUND> directory. This sample source code demonstates the procedure used to download a surround preset to the SP2.

Communicating with the SP2

Register 18H of the Control Chip is used to interface with the SP2 Surround Processor.

Communication with the SP2 is done using a bit-serial protocol.

Modifying a register value to the SP2 involves sending a "register address - register value" pair to the SP2 using a special bit-serial protocol through register 18H.

SP2 bit-serial protocol

Bit 0 of register 18H is the Data Bit (DATA).

Bit 1 of register 18H is the Clock Bit (CLK).

Bit 2 of register 18H is the Address Latch Bit (ADR).

Each bit of a message is sent to the SP2 by first sending a byte with the CLK bit low.

The message bit is sent in a byte with CLK low and the DATA bit containing the desired bit value.

By sending a third byte with CLK high, and DATA set to the correct value, the bit is "latched" into the SP2.

The ADR bit is used to differentiate the register-address-register value parts of the message.

When the bytes related to the register address part of the message are sent, ADR should be low. When all 8 bits of the address have been sent, a bit should be sent with ADR high, to latch the register address to the SP2.

ADR should then be high while the bytes related to the register value part of the message is sent.

Finally a last byte with ADR low should be sent, to latch the register value part of the message.

Sample code on how this procedure is accomplished is supplied on the Developer Toolkit diskette (in directory SURROUND).

While communicating with the SP2, we reccomend that interrupts be disabled, in order to avoid access conflicts with background applications that could access the OPL3 chip or the Control Chip.

YM7128

Surround Processor (SP2)

OUTLINE

This is an LSI which has quality digital surround sound capabilities realized by Yamaha's digital audio technology. The LSI has built-in A/D and D/A converters which enable digital surround sound processing for analog input/output. Its eight digital delay lines may provide delay time of up to 100 msec. for each, and digital adding up of delay line signals for two-channel output assures a wide range of application.

FEATURES

• The built-in RAM realizes digital delay time of 100 msec. * at the maximum.

• Feedback loop can be constructed for reverberation.

• Various surround effect can be obtained by controlling this LSI with serial data from microprocessor.

• Digital attenuator is built in for surround sound volume control.

• Sampling frequency is 23.6 kHz * , and 14 bit floating A/D converter is built in.

• Two-times oversampling digital filter and 14 bit floating D/A converter are built in.

• 16 pin DIP package, silicone gate CMOS 5V power supply.

PIN CONFIGURATIONS

TOP VIEW

PIN DESCRIPTIONS

+; pulled up

BLOCK DIAGRAM

FUNCTION DESCRIPTION

As shown in the block diagram, analog signal input at AIN terminal are converted to 14 bit digital signal with the sampling frequency of 28.6 kHz using 14 bit floating type A/D converter, and then attenuated by the digital attenuator VM. Tap T0 output of digital delay passes through first order FIR type low pass filter and attenuated by VC. These signals are added before they are input to digital delay. Digital delay has nine output taps and tap positions can be switched by the registers T0 to T8. Outputs of eight taps from T1 to T8 are attenuated and added for each channel with the digital attenuator from GL1 to GL8 and GR1 to GR8 respectively, and attenuated by digital attenuator VL or VR to be input to two-times oversampling digital filter. Since this filter attenuates aliasing noise, it reduces the burden on external analog low pass-filter. Digital input to D/A converter shall be with doubled value, which is 47.1 kHz sampling rate.

MICROPROCESSOR INTERFACE

Digital attenuation value, delay time and FIR type low pass filter coefficients are all set by writing data into registers.

With A0 = 'L", 8 bit address data are sent synchronizing with SCI. At the rising edge of A0, register address is taken in. With A0 = 'H", 8 bit data are sent synchronizing with SCI, then register data are changed at the falling edge of A0.

• At the time of initial clear, VM, VC, VL and VR registers are reset to 0. Other register values are not fixed.

REGISTER MAP

Note 1) x; Don't Care

Note 2) Don't write to the other address

REGISTER DATA DESCRIPTION

(1) Attenuation value setting (GL1 to GL8, GR1 to GR8, VM, VC, VL, VR)

• Output polarity (bit 5)

When bit 5 - "1": Output signal is in phase with input signal.

When bit 5 = "0": Output signal is reversed phase with input signal.

• Attenuation value (bit 4-0)

(2) Delay time setting (T0 to T8) (XI=7.16 MHz)

(3) FIR Low Pass Filter coefficient setting (C0, C1).

The lower 6 bits of coefficient register are used as the upper 6 bits of 12 bit 2's compliment data actually processed inside.

Decimal point

SYSTEM BLOCK DIAGRAM

EXTERNAL DIMENSIONS

ELECTRICAL CHARACTERISTICS

• Absolute maximum ratings

• Recommended operating conditions

• DC characteristics (Conditions: $\mathrm{Ta}=25^{\circ }\mathrm{C},$ $\mathrm{VDD}=5.0\mathrm{V}$)

Note 1: Applicable to the input terminals except XI Note 2: Applicable to XI terminal

• AC characteristics (Conditions: $\mathrm{Ta}=25^{\circ }\mathrm{C},{\mathrm{V}}_{\mathrm{DD}}=5.0\mathrm{V})$

• ANALOG characteristics (Conditions: $\mathrm{Ta}=25^{\circ }\mathrm{C},{\mathrm{V}}_{\mathrm{DD}}=5.0\mathrm{V})$

Note) 0dB=1.5Vrms

REFERENCE CHARACTERISTICS 2 times oversampling filter

FREQUENCY

Output vs THD+NOISE

OUTPUT [Vrms]

The specifications of this product are subject to improvement changes without prior notice.

YAMAHA CORPORATION

Address inquiries to: Semi-conductor Sales Department

Head Office 203. Matsunokijima, Toyooka-mura, Iwata-gun, Shizuoka-ken, 438-01 Electronic Equipment business section Tel. 0639-62-4918 Fax. 0639-62-5054

Tokyo Office 8-4, Surugadal Kanda, Chlyoda-ku,

Tokyo, 101

Ryumeikan Bldg. 4F

Tel. 03-265-4481 Fax. 03-255-4488

Osaka Office 3-12-9, Minami Senba, Chuo-ku.

Osaka City, Osaka, 642

Shinsaibashi Plaza Bldg. 4F

Tel. 08-252-7980 Fax. 08-252-5615

U.S.A. YAMAHA Systems Technology. 652 Ridder Park Drive San Jose, CA95131 Tel. 408-437-3133 Fax. 408-437-8791

The following source code demonstrates how to program a Surround preset.

Function Write_Srnd_Reg writes the specified value to the YM7128 through the control chip register 18H. The sample code assumes that the control chip is located at address 38AH.

Function Write_Surround sends the 32 bytes of a suuround preset to the YM7128 using the bit-serial protocol. For each byte of the Surround preset, the register number (variable addr) is sent first , followed by the register value (variable data).

/*

    SURR.C

    Write a preset to the surround chip.

    Copyright 1992, Ad Lib Inc.

*/

unsigned control_io = 0x38a;        /* address of control chip section */

/* Write 'val' to the surround register in the control chip. */

static void _fastcall Write_Srnd_Reg (unsigned val)

{

    _asm {

        mov     dx, control_io

l10:

            in     al, dx

            test    al, 0c0h          ;status bits indicating chip is busy

            jnz     l10

            mov     ax, 18h          ;surround register number

            out     dx, al

            mov     ax, val

            inc     dx

            out     dx, al

    }

}

/* NOTE: When writing a byte to the control chip, it is very important that the transfer not be interrupted. Therefore, interrupts are disabled while the preset is being sent. */

void Write_Surround (unsigned char *preset);

{

unsigned addr, data, cmd;

int i, k;

_asm {

    pushf                        ;preserve the current interrupt state

    push     dx

    cli                        ;disable interrupts

    mov       dx, control_io

    mov       al, 0ffh            ;disable OPL3, enable control bank

    out       dx, al

}

/* Send the 31 array elements: */

for (i = 0; i < 31; i++) {

    cmd = 0;                        /* clock LOW, A0 LOW */

    addr = i;

    for (k = 7; k >= 0; k--) {

        cmd &= ~2;                    /* clock LOW */

        Write_Srnd_Reg (cmd);

        cmd = (cmd & ~1) | ((addr >> k) & 1);

        Write_Srnd_Reg (cmd);

        cmd |= 2;                    /* clock HIGH */

        Write_Srnd_Reg (cmd);

    }

    cmd |= 4;                        /* Set A0 to 1 */

    Write_Srnd_Reg (cmd);

    data = preset [i];

    for (k = 7; k >= 0; k--) {

        cmd &= ~2;                    /* clock LOW */

        Write_Srnd_Reg (cmd);

        cmd = (cmd & ~1) | ((data >> k) & 1);

        Write_Srnd_Reg (cmd);

        cmd |= 2;                    /* clock HIGH */

        Write_Srnd_Reg (cmd);

    }

    cmd &= ~4;                        /* Set A0 to 0 */

    Write_Srnd_Reg (cmd);

}

_asm {

    mov       dx, control_io

120:

    in       al, dx

    test     al, 0c0h            ;status bits indicating chip is busy

    jnz      l20

    mov       al, 0feh            ;enable OPL3, disable control bank

    out      dx, al

    pop      dx

    popf        ;restore previous interrupt state

}

}

Ad Lib Gold © Ad Lib Inc.1992 Confidential Mon, Mar 23,1992

PIN OUT FOR JOYSTICK-MIDI CONNECTOR OF THE Ad Lib GOLD CARD